The present invention relates to disk drive read/write channels and, particularly, to a system and method for write precompensation using phase interpolation techniques.
In hard disk drives, data is written on magnetic media by induction of magnetic fields caused by passing a current through the thin film head inductor. Ones and zeros are written on the media as magnetic field transitions. When two magnetic field transitions occur too closely to one another, the demagnetization field from an already-written transition causes a non-linear distortion or shift in the bit location of the next transition. This distortion or shift is referred to as non-linear bit shift.
Non-linear bit shift is compensated through a technique referred to as write precompensation. Write precompensation is illustrated in FIG. 1. A magnetic medium 10 is shown. A previous transition has been written at 12. The next transition should be written at 14. However, if it is written at 14, the previous transition will attract it and it will be written earlier, at 16, with a shift of T. Write precompensation determines a period t after time 14 to write the next transition at 18. The transition at 18 will be attracted to the previous transition and will be written at the desired correct time 14.
The period t is relatively small, and in particular, is smaller than can be resolved using the system""s phase locked loop (PLL). As such, there is a need for an improved, high resolution write precompensation circuit.
A write precompensation circuit according to the present invention employs a phase blender to increase the resolution of the output phases of a phase locked loop circuit. According to one implementation, eight phases from a PLL phase oscillator are received as inputs into a bank of four phase blenders. The phase blenders output a 0%, 25%, 50%, or 75% interpolation to the adjacent phases. A multiplexer is then used to select which of the phase outputs is used for the write precompensation. According to one implementation, a reference and three delay clocks are provided. Each delay is programmable by a five bit number and the actual delay is performed by selecting one of eight input phases or an interpolation thereof.